// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  sao_reg_offset_field.h
// Project line  :  K3
// Department    :  K3
// Author        :  Huawei
// Version       :  V100
// Date          :  2015/4/10
// Description   :  HiVcodecV100 VDEC
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/04/10 10:02:42 Create file
// ******************************************************************************

#ifndef __SAO_REG_OFFSET_FIELD_H__
#define __SAO_REG_OFFSET_FIELD_H__

#define SAO_SND_CUR_ST_LEN        4
#define SAO_SND_CUR_ST_OFFSET     20
#define SAO_BPS_CUR_ST_LEN        4
#define SAO_BPS_CUR_ST_OFFSET     16
#define SAO_CAL_CUR_ST_LEN        8
#define SAO_CAL_CUR_ST_OFFSET     8
#define SAO_LD_DATA_CUR_ST_LEN    4
#define SAO_LD_DATA_CUR_ST_OFFSET 4
#define SAO_LD_INFO_CUR_ST_LEN    4
#define SAO_LD_INFO_CUR_ST_OFFSET 0

#define SAO_LD_DATA_LEFT_LINE_CNT_LEN    4
#define SAO_LD_DATA_LEFT_LINE_CNT_OFFSET 24
#define SAO_LD_DATA_LINE_CNT_LEN         4
#define SAO_LD_DATA_LINE_CNT_OFFSET      20
#define SAO_CTB_Y_LEN                    8
#define SAO_CTB_Y_OFFSET                 12
#define SAO_CTB_X_LEN                    8
#define SAO_CTB_X_OFFSET                 4
#define SAO_BLK_IN_CTB_CNT_LEN           4
#define SAO_BLK_IN_CTB_CNT_OFFSET        0

#define SAO_STACK_CUR_FULL_LEN            1
#define SAO_STACK_CUR_FULL_OFFSET         22
#define SAO_STACK_CUR_FULL_PRE_LEN        1
#define SAO_STACK_CUR_FULL_PRE_OFFSET     21
#define SAO_LD_STRACK_WPTR_CNT_PRE_LEN    9
#define SAO_LD_STRACK_WPTR_CNT_PRE_OFFSET 12
#define SAO_LD_STRACK_WPTR_CNT_LEN        8
#define SAO_LD_STRACK_WPTR_CNT_OFFSET     4
#define SAO_LD_STACK_WPTR_LEN             4
#define SAO_LD_STACK_WPTR_OFFSET          0

#define SAO_BPS_STACK_RPTR_CNT_LEN    8
#define SAO_BPS_STACK_RPTR_CNT_OFFSET 8
#define SAO_BPS_STACK_RPTR_LEN        4
#define SAO_BPS_STACK_RPTR_OFFSET     4
#define SAO_BPS_LINE_CNT_LEN          4
#define SAO_BPS_LINE_CNT_OFFSET       0

#define SAO_CAL_COL_CNT_LEN               4
#define SAO_CAL_COL_CNT_OFFSET            16
#define SAO_CAL_LINE_CNT_LEN              4
#define SAO_CAL_LINE_CNT_OFFSET           12
#define SAO_CAL_STACK_CUR_RPTR_LEN        4
#define SAO_CAL_STACK_CUR_RPTR_OFFSET     8
#define SAO_CAL_STACK_CUR_RPTR_CNT_LEN    8
#define SAO_CAL_STACK_CUR_RPTR_CNT_OFFSET 0

#define SAO_STACK_LEFT_FULL_PRE_LEN        1
#define SAO_STACK_LEFT_FULL_PRE_OFFSET     22
#define SAO_STACK_LEFT_FULL_LEN            1
#define SAO_STACK_LEFT_FULL_OFFSET         21
#define SAO_STACK_EMPTY_LEN                1
#define SAO_STACK_EMPTY_OFFSET             20
#define SAO_SND_LEFT_STACK_RPTR_LEN        4
#define SAO_SND_LEFT_STACK_RPTR_OFFSET     16
#define SAO_SND_LEFT_STACK_RPTR_CNT_LEN    8
#define SAO_SND_LEFT_STACK_RPTR_CNT_OFFSET 8
#define SAO_SND_LEFT_LINE_CNT_LEN          4
#define SAO_SND_LEFT_LINE_CNT_OFFSET       4
#define SAO_SND_TOP_CNT_LEN                4
#define SAO_SND_TOP_CNT_OFFSET             0

#define SAO_RD_NBR_BUF_CUR_ST_LEN     4
#define SAO_RD_NBR_BUF_CUR_ST_OFFSET  12
#define SAO_WR_NBR_EMAR_CUR_ST_LEN    4
#define SAO_WR_NBR_EMAR_CUR_ST_OFFSET 8
#define SAO_RD_EMAR_CUR_ST_LEN        4
#define SAO_RD_EMAR_CUR_ST_OFFSET     4
#define SAO_WR_BUF_CUR_ST_LEN         4
#define SAO_WR_BUF_CUR_ST_OFFSET      0

#define SAO_NBR_CTBY_LEN       8
#define SAO_NBR_CTBY_OFFSET    12
#define SAO_NBR_CTBX_LEN       8
#define SAO_NBR_CTBX_OFFSET    4
#define SAO_TOP_BLK_VLD_LEN    4
#define SAO_TOP_BLK_VLD_OFFSET 0

#define SAO_WSTACK_FULL_PRE_LEN    1
#define SAO_WSTACK_FULL_PRE_OFFSET 17
#define SAO_WSTACK_EMPTY_LEN       1
#define SAO_WSTACK_EMPTY_OFFSET    16
#define SAO_WSTACK_WPTR_PRE_LEN    4
#define SAO_WSTACK_WPTR_PRE_OFFSET 12
#define SAO_WSTACK_WPTR_LEN        4
#define SAO_WSTACK_WPTR_OFFSET     8
#define SAO_WSTACK_RPTR_LEN        4
#define SAO_WSTACK_RPTR_OFFSET     4
#define SAO_WR_COLOR_INDEX_LEN     4
#define SAO_WR_COLOR_INDEX_OFFSET  0

#define SAO_WR_TILE_RIGHT_CTBX_LEN         8
#define SAO_WR_TILE_RIGHT_CTBX_OFFSET      24
#define SAO_NBR2OBUF_LEFT_RADDR)CNT_LEN    8
#define SAO_NBR2OBUF_LEFT_RADDR)CNT_OFFSET 16
#define SAO_SAO2EMAR_LEFT_AWVALID_LEN      1
#define SAO_SAO2EMAR_LEFT_AWVALID_OFFSET   15
#define SAO_EMAR2SAO_LEFT_AWREADY_LEN      1
#define SAO_EMAR2SAO_LEFT_AWREADY_OFFSET   14
#define SAO_SAO2EMAR_LEFT_WVALID_LEN       1
#define SAO_SAO2EMAR_LEFT_WVALID_OFFSET    13
#define SAO_EMAR2SAO_LEFT_WREADY_LEN       1
#define SAO_EMAR2SAO_LEFT_WREADY_OFFSET    12
#define SAO_EMAR_LEFT_AWVLD_CNT_LEN        4
#define SAO_EMAR_LEFT_AWVLD_CNT_OFFSET     8
#define SAO_EMAR_LEFT_WVLD_CNT_LEN         8
#define SAO_EMAR_LEFT_WVLD_CNT_OFFSET      0

#define SAO_NBR2OBUF_LEFT_RREQ_LEN             1
#define SAO_NBR2OBUF_LEFT_RREQ_OFFSET          27
#define SAO_OBUF2NBR_RACK_LEN                  1
#define SAO_OBUF2NBR_RACK_OFFSET               26
#define SAO_NBR2NBUF_TOP_RREQ_LEN              1
#define SAO_NBR2NBUF_TOP_RREQ_OFFSET           25
#define SAO_NBUF2NBR_RACK_LEN                  1
#define SAO_NBUF2NBR_RACK_OFFSET               24
#define SAO_NBR2NBUF_TOP_RADDR_CNT_LEN         8
#define SAO_NBR2NBUF_TOP_RADDR_CNT_OFFSET      16
#define SAO_SAO2EMAR_TOP_AWVALID_LEN           1
#define SAO_SAO2EMAR_TOP_AWVALID_OFFSET        15
#define SAO_EMAR2SAO_TOP_AWREADY_LEN           1
#define SAO_EMAR2SAO_TOP_AWREADY_OFFSET        14
#define SAO_SAO2EMAR_TOP_WVALID_LEN            1
#define SAO_SAO2EMAR_TOP_WVALID_OFFSET         13
#define SAO_EMAR2SAO_TOP_WREADY_LEN            1
#define SAO_EMAR2SAO_TOP_WREADY_OFFSET         12
#define SAO_EMAR_TOP_WVLD_CNT_LEN              8
#define SAO_EMAR_TOP_WVLD_CNT_OFFSET           4
#define SAO_EMAR_TOP_WVLD_IN_WSTACK_CNT_LEN    4
#define SAO_EMAR_TOP_WVLD_IN_WSTACK_CNT_OFFSET 0

#define SAO_EMAR2SAO_AWREADY_LEN         1
#define SAO_EMAR2SAO_AWREADY_OFFSET      31
#define SAO_EMAR2SAO_WREADY_LEN          1
#define SAO_EMAR2SAO_WREADY_OFFSET       30
#define SAO_SAO2EMAR_AWVALID_LEN         1
#define SAO_SAO2EMAR_AWVALID_OFFSET      29
#define SAO_SAO2EMAR_WVALID_LEN          1
#define SAO_SAO2EMAR_WVALID_OFFSET       28
#define SAO_RD_OBUF_CUR_ST_LEN           4
#define SAO_RD_OBUF_CUR_ST_OFFSET        24
#define SAO_WR_EMAR_CUR_ST_LEN           4
#define SAO_WR_EMAR_CUR_ST_OFFSET        20
#define SAO_STACK_LUMA_WPTR_PRE_LEN      4
#define SAO_STACK_LUMA_WPTR_PRE_OFFSET   16
#define SAO_STACK_CHROMA_WPTR_PRE_LEN    4
#define SAO_STACK_CHROMA_WPTR_PRE_OFFSET 12
#define SAO_STACK_LUMA_RPTR_LEN          4
#define SAO_STACK_LUMA_RPTR_OFFSET       8
#define SAO_STACK_CHROMA_RPTR_LEN        4
#define SAO_STACK_CHROMA_RPTR_OFFSET     4
#define SAO_STACK_LUMA_EMPTY_LEN         1
#define SAO_STACK_LUMA_EMPTY_OFFSET      3
#define SAO_STACK_LUMA_FULL_PRE_LEN      1
#define SAO_STACK_LUMA_FULL_PRE_OFFSET   2
#define SAO_STACK_CHROMA_EMTPY_LEN       1
#define SAO_STACK_CHROMA_EMTPY_OFFSET    1
#define SAO_STACK_CHROMA_FULL_PRE_LEN    1
#define SAO_STACK_CHROMA_FULL_PRE_OFFSET 0

#define SAO_CTBX_LEN            8
#define SAO_CTBX_OFFSET         24
#define SAO_CTBY_LEN            8
#define SAO_CTBY_OFFSET         16
#define SAO_WR_EMAR_CTBX_LEN    8
#define SAO_WR_EMAR_CTBX_OFFSET 8
#define SAO_WR_EMAR_CTBY_LEN    8
#define SAO_WR_EMAR_CTBY_OFFSET 0

#define SAO_SAO2EMAR_AWCOEF2_LEN    16
#define SAO_SAO2EMAR_AWCOEF2_OFFSET 16
#define SAO_SAO2EMAR_AWCOEF3_LEN    16
#define SAO_SAO2EMAR_AWCOEF3_OFFSET 0

#define SAO_SAO2EMAR_AWCOEF4_LEN    32
#define SAO_SAO2EMAR_AWCOEF4_OFFSET 0

#define SAO_OBUF_WPTR_LEN                     4
#define SAO_OBUF_WPTR_OFFSET                  24
#define SAO_OBUF_WHOLE_WPTR_LEN               4
#define SAO_OBUF_WHOLE_WPTR_OFFSET            20
#define SAO_OBUF_RPTR_LEN                     4
#define SAO_OBUF_RPTR_OFFSET                  16
#define SAO_OBUF_FULL_LEN                     1
#define SAO_OBUF_FULL_OFFSET                  13
#define SAO_OBUF_EMPTY_LEN                    1
#define SAO_OBUF_EMPTY_OFFSET                 12
#define SAO_OBUF_CORE_TILE_RIGHT_FULL_LEN     1
#define SAO_OBUF_CORE_TILE_RIGHT_FULL_OFFSET  11
#define SAO_OBUF_CORE_TILE_RIGHT_EMPTY_LEN    1
#define SAO_OBUF_CORE_TILE_RIGHT_EMPTY_OFFSET 10
#define SAO_OBUF_NBR_TILE_RIGHT_FULL_LEN      1
#define SAO_OBUF_NBR_TILE_RIGHT_FULL_OFFSET   9
#define SAO_OBUF_NBR_TILE_RIGHT_EMPTY_LEN     1
#define SAO_OBUF_NBR_TILE_RIGHT_EMPTY_OFFSET  8
#define SAO_OBUF2CORE_RECONSTR_WACK_LEN       1
#define SAO_OBUF2CORE_RECONSTR_WACK_OFFSET    7
#define SAO_OBUF2LDSTR_RACK_LEN               1
#define SAO_OBUF2LDSTR_RACK_OFFSET            6
#define SAO_OBUF2CORE_TILE_RIGHT_WACK_LEN     1
#define SAO_OBUF2CORE_TILE_RIGHT_WACK_OFFSET  5
#define SAO_OBUF2CORE_RACK_LEN                1
#define SAO_OBUF2CORE_RACK_OFFSET             4
#define SAO_OBUF2NBR_WACK_LEN                 1
#define SAO_OBUF2NBR_WACK_OFFSET              2
#define SAO_OBUF2NBR_RACK_LEN                 1
#define SAO_OBUF2NBR_RACK_OFFSET              1
#define SAO_OBUF2CORE_WACK_LEN                1
#define SAO_OBUF2CORE_WACK_OFFSET             0

#define SAO_SAO2PMV_WACK_LEN           1
#define SAO_SAO2PMV_WACK_OFFSET        25
#define SAO_SAO2DBLK_WACK_LEN          1
#define SAO_SAO2DBLK_WACK_OFFSET       24
#define SAO_IBUF2CORE_DBLK_RACK_LEN    1
#define SAO_IBUF2CORE_DBLK_RACK_OFFSET 22
#define SAO_IBUF2CORE_PMV_RACK_LEN     1
#define SAO_IBUF2CORE_PMV_RACK_OFFSET  21
#define SAO_IBUF2NBR_PMV_RACK_LEN      1
#define SAO_IBUF2NBR_PMV_RACK_OFFSET   20
#define SAO_IBUF_DBLK_WPTR_LEN         2
#define SAO_IBUF_DBLK_WPTR_OFFSET      18
#define SAO_IBUF_DBLK_RPTR_LEN         2
#define SAO_IBUF_DBLK_RPTR_OFFSET      16
#define SAO_IBUF_DBLK_FULL_LEN         1
#define SAO_IBUF_DBLK_FULL_OFFSET      13
#define SAO_IBUF_DBLK_EMPTY_LEN        1
#define SAO_IBUF_DBLK_EMPTY_OFFSET     12
#define SAO_IBUF_DBLK_CMD_WPTR_LEN     4
#define SAO_IBUF_DBLK_CMD_WPTR_OFFSET  8
#define SAO_IBUF_DBLK_CMD_RPTR_LEN     4
#define SAO_IBUF_DBLK_CMD_RPTR_OFFSET  4
#define SAO_IBUF_PMV_FULL_LEN          1
#define SAO_IBUF_PMV_FULL_OFFSET       3
#define SAO_IBUF_PMV_EMTPY_LEN         1
#define SAO_IBUF_PMV_EMTPY_OFFSET      2
#define SAO_IBUF_NBR_PMV_FULL_LEN      1
#define SAO_IBUF_NBR_PMV_FULL_OFFSET   1
#define SAO_IBUF_NBR_PMV_EMPTY_LEN     1
#define SAO_IBUF_NBR_PMV_EMPTY_OFFSET  0

#define SAO_NBUF_CORE_TOP_FULL_LEN     1
#define SAO_NBUF_CORE_TOP_FULL_OFFSET  11
#define SAO_NBUF_CORE_TOP_EMPTY_LEN    1
#define SAO_NBUF_CORE_TOP_EMPTY_OFFSET 10
#define SAO_NBUF_NBR_TOP_FULL_LEN      1
#define SAO_NBUF_NBR_TOP_FULL_OFFSET   9
#define SAO_NBUF_NBR_TOP_EMPTY_LEN     1
#define SAO_NBUF_NBR_TOP_EMPTY_OFFSET  8
#define SAO_CORE2NBUF_WREQ_LEN         1
#define SAO_CORE2NBUF_WREQ_OFFSET      7
#define SAO_NBUF2CORE_WACK_LEN         1
#define SAO_NBUF2CORE_WACK_OFFSET      6
#define SAO_CORE2NBUF_RREQ_LEN         1
#define SAO_CORE2NBUF_RREQ_OFFSET      5
#define SAO_NBUF2CORE_RACK_LEN         1
#define SAO_NBUF2CORE_RACK_OFFSET      4
#define SAO_NBR2NBUF_WREQ_LEN          1
#define SAO_NBR2NBUF_WREQ_OFFSET       3
#define SAO_NBUF2NBR_WACK_LEN          1
#define SAO_NBUF2NBR_WACK_OFFSET       2
#define SAO_NBR2NBUF_RREQ_LEN          1
#define SAO_NBR2NBUF_RREQ_OFFSET       1
#define SAO_NBUF2NBR_RACK_LEN          1
#define SAO_NBUF2NBR_RACK_OFFSET       0

#endif // __SAO_REG_OFFSET_FIELD_H__
